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Symposium III: Dry & Wet Etch and Cleaning

Opening Remarks

Ying Zhang

Naura
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Oral Session
Poster Session

The fast changing and advancing scaling technique and potential device infrastructure

David Xiao

Shanghai Integrated Circuit Research and Develop (ICRD) Center

3D NAND Technology Cost Scaling Challenges and Solutions

Richard Yang

Fortune Precision Corp, Shenyang

Role of underlayers in novel patterning for EUV lithography

Douglas Guerrero

Brewer Science, Inc.

Considerations in seting up industry standards for photolithography process, historical perspectives, methologies, and outlook

Qiang Wu

Fudan University

Profile control technique for High Aspect Contact Etch utilizing Coverage Controllable ALD

Yoshihide Kihara

TEL

Pitch Walking Simulation and Process Window Evaluation of Self-Aligned Quadruple Patterning for Advanced Nodes

Xing Ke

SMIC

Optimization of approach for metal contamination reduction

Xing-Jun Yao

Beijing NAURA Microelectronics Equipment Co. Ltd

High aspect ratio etch challenges and proposed ICP etch solutions

Zhiqiang Liu

AMEC

THE COMBINATION OF WF6 AND HBR FOR HIGH-ASPECT-RATIO CRYOGENIC DIELECTRIC ETCH

Vina Xu

AMEC

Approach for High transmission ratio power device pad etch with smooth sidewall and long MTBC

Dongming Zhou

AMEC

Mattson Novyka Selective Etch and Applications

Shanyu Wang

Mattson

SADP etch process development using PR core for sub 17nm DRAM

Li Tian Xu

Beijing NAURA Microelectronics Equipment Co. Ltd

Beyond 20nm DRAM Capacitor Etch Challenge and Process Solution

Zengwen Hu

AMEC

Localized Pattern Loading Improvement of SOC Recess Process for Airgap Spacer

Bo Su

Semiconductor Manufacturing International Corporation(SMIC)

Integrated etch solution for magnetic tunneling junction patterning

Yuxin Yang

Leuven Instruments

An Explanation of Wafer Center Arcing Defect

Jun Wang

Semiconductor Manufacturing North China (Beijing) Corporation(SMNC)

Hard mask etch process development for patterning 60nm magnetic tunnel junction

Xiaohui Li

Naura

200/150/100mm Compatible, ICP and CCP Etch Total Solutions

Yiming Zhang

Naura, China

Trench Etch for SiC Power Devices

Qiushi Xie

Beijing NAURA Microelectronics Equipment Co. Ltd

Removing (sub)surface defects induced by Si wafer thinning processes enables high-performance backscattered electron detector

Zhu Chen

Shanghai University

Effectively improving local critical dimension uniformity of small hole arrays by photo resist treatment

Mimi Dai

Advanced Micro-Fabrication Equipment Inc. China

Advanced Ru Selective Etch for MEMS and Sub-3nm Applications

Chien-Pin Sherman HSU

Avantor
Tri layer mask dry etch process optimizing and wet effect for straight profile

Xiaobing Liu

Shanghai IC R&D Center

IMPROVING CIS WHITE PIXEL PERFORMANCE BY RAP PROCESS REPLACEMENT ON SYNDION FS TOOL IN VERTICAL TRANSFER GATE APPLICATION

Yiling Sun

Lam Research

Effects of Ion incident angles on Etching Morphology of Blazed Grating by IBE

Jie Yuan

Jiangsu Normal University

Balance of Spacer Profile Angle and Footing to Reduce Pitch Walking in SADP Process

Chun Kai Wang

Lam Research

Investigation of Fin Bowing Formation Mechanism During STI Etching by Virtual Fabrication

Li Fei Sun

Lam Research

PROCESS WINDOW CHECK FOR FIN CUT FIRST SCHEME

Li Fei Sun

Lam Research

Surface Modification Detection by Lam Spectral Reflectometer System

Caigan Chen

Lam Research

Recipe Optimization to Reduce Arching and DA Shift Risk under Wafer Backside Dielectric Layers

Bill Bian

Lam Research

PSR Silicon Trench Profile Optimization in FinFET Fabrication

Zhengning Li

Semiconductor Manufacturing International Corporation(SMIC)

Investigation of Selective SiGe Etching Process for Advanced Semiconductor Technology

Peng Yang

Shanghai IC R&D Center

A Study on Impact of Gate Thickness on Device Performance for Advanced Node Logic Transistors

Xu Jia

Lam Research

The Effects of Etch Stop Layer Undercut on BEOL Electric Performance at Advance Node

Tianhao Zhang

Lam Research

Impact of Metal Line Roughness on RC Delay

Hexin Zhou

Lam Research

Study on Inversed-taper Poly Profile as Solution of 3D Corner Residue

PengFei Lyu

Lam Research

Simulation Study on Different Integration Schemes to Form Single Diffusion Break

PengFei Lyu

Lam Research

Study on Process Improvement and Yield Enhancement of 40nm e-flash AIO Wet Strip

Zhiyuan Xu

HLMC

Study and Optimazation of Photo Resistor Etch Back loop in HK Metal Gate

Yajie Li

HLMC

STUDY ON THE OPTIMIZATION OF FINFET ULTRA-SHALLOW JUNCTION ION IMPLANTATION PROCESS

Wenqiang Li

HLMC

N/P SPLIT BOUNDARY PROFILE IMPROVEMENT IN HIGH K METAL GATE DUMMY POLY REMOVE PROCESS

Huang Shan

HLMC

Exploration and Optimization of Metal Gate Etch Back Process in Advanced Technology Node

Shaoxiong Liu

HLMC

Advanced Pulsing Control Tungsten Profile in DRAM Periphery Gate Etch

Zheng Ruan

Lam Research

Statistic big data analysis method used for Tilting mismatch problem solving

Rui Bao

Lam Research

Conductor Etch Advanced Function for sub-20nm DRAM Patterning:LWR Improvement

Yujia Zhong

Lam Research

15nm DRAM SADP patterning solution by capacitively coupled plasma etcher

Julia Zheng

Lam Research

Selective Wet-etching of GeSi in Multi-layer GeSiSi Stacks

Jiajia Tian

Integrated Circuits Advanced Process R&D Center of IMECAS

STUDY ON IMPACT OF SOURCE DRAIN RECESS PROFILE ON EPI SIZE FOR ADVANCED FINFET

Minxiang Wang

Lam Research

Via Contact Profile Effect on Metal-Via Resistance & Overlay Window

Jian Huang

Lam Research

Enhanced Passivation on Carbon Sidewall to Control Bowing During Hard Mask Open Etch Process

Arthur Jin

Lam Research

Profile Improvement in Aluminum Oxide Etch

Yingying Zhou

Lam Research

Hole Micro Twisting Improvement in a High Aspect Ratio Carbon Etch

Swen Jin

Lam Research

Hole Micro Uniformity Improvement in a High Aspect Ratio Carbon Etch

YaQian Jiang

Lam Research

Hole shape modification in high aspect ratio carbon etch process

Junming Wang

Lam Research

Notching Reduction by Pulsed Low Frequency Bias Power during Deep Silicon Etch on SOI Substrate

Stan Zhang

Lam Research

Wafer Extreme Edge Feature Tilting Improvement

Shanshan Nie

Lam research

Temperature Controlled Dry Etch Trim Process for Silicon Film Planarization

Tao (McRee) Wang

Lam Research

Optimization of approach for metal contamination reduction

Meng-Yu Xie

NAURA

Optimization of Shallow Trench Isolation CD micro loading in advance CMOS

Guang Yang

NAURA

Research of ultra high aspect ratio silicon etching in 1y DRAM STI

Zheng Ji

NAURA

SNC SADP Spacer etch process development using carbon hard mask mandrel for sub advanced process DRAM

Hao Liu

NAURA

Silicon Partial Etch Defect Researches in BSI CMOS Image Sensor Process Product

Hebao Liu

SMIC

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Symposium III: Dry & Wet Etch and Cleaning

Symposium III: Dry & Wet Etch and Cleaning

Opening Remarks

Ying Zhang

Oral Session

Poster Session

The fast changing and advancing scaling technique and potential device infrastructure

3D NAND Technology Cost Scaling Challenges and Solutions

Role of underlayers in novel patterning for EUV lithography

Considerations in seting up industry standards for photolithography process, historical perspectives, methologies, and outlook

Profile control technique for High Aspect Contact Etch utilizing Coverage Controllable ALD

Pitch Walking Simulation and Process Window Evaluation of Self-Aligned Quadruple Patterning for Advanced Nodes

Optimization of approach for metal contamination reduction

High aspect ratio etch challenges and proposed ICP etch solutions

THE COMBINATION OF WF6 AND HBR FOR HIGH-ASPECT-RATIO CRYOGENIC DIELECTRIC ETCH

Approach for High transmission ratio power device pad etch with smooth sidewall and long MTBC

Mattson Novyka Selective Etch and Applications

SADP etch process development using PR core for sub 17nm DRAM

Beyond 20nm DRAM Capacitor Etch Challenge and Process Solution

Localized Pattern Loading Improvement of SOC Recess Process for Airgap Spacer

Integrated etch solution for magnetic tunneling junction patterning

An Explanation of Wafer Center Arcing Defect

Hard mask etch process development for patterning 60nm magnetic tunnel junction

200/150/100mm Compatible, ICP and CCP Etch Total Solutions

Trench Etch for SiC Power Devices

Removing (sub)surface defects induced by Si wafer thinning processes enables high-performance backscattered electron detector

Effectively improving local critical dimension uniformity of small hole arrays by photo resist treatment

Advanced Ru Selective Etch for MEMS and Sub-3nm Applications

Tri layer mask dry etch process optimizing and wet effect for straight profile

IMPROVING CIS WHITE PIXEL PERFORMANCE BY RAP PROCESS REPLACEMENT ON SYNDION FS TOOL IN VERTICAL TRANSFER GATE APPLICATION

Effects of Ion incident angles on Etching Morphology of Blazed Grating by IBE

Balance of Spacer Profile Angle and Footing to Reduce Pitch Walking in SADP Process

Investigation of Fin Bowing Formation Mechanism During STI Etching by Virtual Fabrication

PROCESS WINDOW CHECK FOR FIN CUT FIRST SCHEME

Surface Modification Detection by Lam Spectral Reflectometer System

Recipe Optimization to Reduce Arching and DA Shift Risk under Wafer Backside Dielectric Layers

PSR Silicon Trench Profile Optimization in FinFET Fabrication

Investigation of Selective SiGe Etching Process for Advanced Semiconductor Technology

A Study on Impact of Gate Thickness on Device Performance for Advanced Node Logic Transistors

The Effects of Etch Stop Layer Undercut on BEOL Electric Performance at Advance Node

Impact of Metal Line Roughness on RC Delay

Study on Inversed-taper Poly Profile as Solution of 3D Corner Residue

Simulation Study on Different Integration Schemes to Form Single Diffusion Break

Study on Process Improvement and Yield Enhancement of 40nm e-flash AIO Wet Strip

Study and Optimazation of Photo Resistor Etch Back loop in HK Metal Gate

STUDY ON THE OPTIMIZATION OF FINFET ULTRA-SHALLOW JUNCTION ION IMPLANTATION PROCESS

N/P SPLIT BOUNDARY PROFILE IMPROVEMENT IN HIGH K METAL GATE DUMMY POLY REMOVE PROCESS

Exploration and Optimization of Metal Gate Etch Back Process in Advanced Technology Node

Advanced Pulsing Control Tungsten Profile in DRAM Periphery Gate Etch

Statistic big data analysis method used for Tilting mismatch problem solving

Conductor Etch Advanced Function for sub-20nm DRAM Patterning:LWR Improvement

15nm DRAM SADP patterning solution by capacitively coupled plasma etcher

Selective Wet-etching of GeSi in Multi-layer GeSiSi Stacks

STUDY ON IMPACT OF SOURCE DRAIN RECESS PROFILE ON EPI SIZE FOR ADVANCED FINFET

Via Contact Profile Effect on Metal-Via Resistance & Overlay Window

Enhanced Passivation on Carbon Sidewall to Control Bowing During Hard Mask Open Etch Process

Profile Improvement in Aluminum Oxide Etch

Hole Micro Twisting Improvement in a High Aspect Ratio Carbon Etch

Hole Micro Uniformity Improvement in a High Aspect Ratio Carbon Etch

Hole shape modification in high aspect ratio carbon etch process

Notching Reduction by Pulsed Low Frequency Bias Power during Deep Silicon Etch on SOI Substrate

Wafer Extreme Edge Feature Tilting Improvement

Temperature Controlled Dry Etch Trim Process for Silicon Film Planarization

Optimization of approach for metal contamination reduction

Optimization of Shallow Trench Isolation CD micro loading in advance CMOS

Research of ultra high aspect ratio silicon etching in 1y DRAM STI

SNC SADP Spacer etch process development using carbon hard mask mandrel for sub advanced process DRAM

Silicon Partial Etch Defect Researches in BSI CMOS Image Sensor Process Product

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