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Symposium I: Device Engineering and Memory Technology

Opening Remarks

Oral Session
Poster Session

Cryogenic CMOS: A New Era for Power-Saving Computing

Qingtai Zhao

Forschungszentrum Jülich | Peter Grünberg Institute

Flip 3D (F3D): A dual-sided integration technology for future's computing hardware

Heng Wu

Peking University

Heterogeneous 3D CFET with Hybrid Channel Configuration

SangHyeon Kim

KAIST

Performance Improvement of Monolithic CFET by Backside Enhanced Contact with C-type Source/Drain Contact Technology

Jie Xu

Institute of Microelectronics, Chinese Academy of Sciences

A SiGe Channel Gate-All-Around Transistor Fabricated Using Novel Cyclic Self-Limiting Wet Etching Combined with Si Removal Process

KaiMin Feng

Institute of Microelectronics, Chinese Academy of Sciences

A Novel Load-Si-cut SOI Nanosheets Transistors with Ultrathin SiGe Cladded Si Channel Structure to Suppress Leakage and Enhance Driven Current

Longyu Sun

Institute of Microelectronics, Chinese Academy of Sciences

The Intergration of SRAM-based Computing in Memory and DRAM-based Prcessing in Memory by 3D Stacking Techniques for AI Large Model Utilization

Hongjie Liu

Shenzhen Reexen Technology Co., Ltd.

RRAM-based In-memory Computing for Intelligent Applications

Zongwei Wang

Peking University

Uncertainty Quantification on Multiscale Modeling of RRAM devices

Ziyan Liao

Sun Yat-sen University

Uniform, Large-Scale, and Robust PECVD-MoS2 Nanograined Memristors

Hyelim Shin

Sungkyunkwan University

Ferroelectric Materials, Devices and Chip Technologies for Enhanced Computational and Storage Capabilities

Xiao Yu

Xidian University

Hafnium-based Ferroelectric Memory and its Neuromorphic Computing Application

Lin Chen

Fudan University

A NOVEL AMBIPOLAR FERROELECTRIC TUNNEL FINFET BASED COMPUTING-IN-MEMORY FOR QUANTIZED NEURAL NETWORKS WITH HIGH AREA- AND ENERGY-EFFICIENCY

Runze Han

Peking University

Z2-FET MEMORY WITH BOTH FLASH AND DRAM MODES

Baitong Tian

Fudan University

Low-Frequency Noise of Vertical Gate-All-Around IGZO FETs

Ying Wu

Huawei Technologies

Defects Characterization and Their Impact on the Stability of Oxide Semiconductor Devices and 2T0C DRAM Cell

Mengwei Si

Shanghai Jiao Tong University

Electrical Characteristics of IGZO Thin Film Transistors Fabricated by Magnetron Sputtering with Controlled Mean Free Path of Sputtered Particles

Kai Chen

Zhejiang University

Novel Low-Dimensional Material-Based Hot Carrier Transistors

Chi Liu

Institute of Metal Research, Chinese Academy of Sciences

Printable Organic Photodetectors for Spectrally Selective Light Sensing

Vincenzo Pecunia

Simon Fraser University, Canada

Addressing Thermal Challenges in SOI with Silicon-On-Silicon Carbide Heterointegration

Junyi Yang

Fudan University

DC and RF Characteristics of Silicon FETs on 55nm Low Power Platform

Gang Wang

GHS Semiconductor

Extract parameters from CV curves using a machine learning method

Wenwen Fei

GHS Semiconductor

Advancing Semiconductor Industry through Atomistic Simulation: A Materials Design Perspective

Xiaoli Liu

Materials Design Inc.
Optimization of the Safe Operation Area in Step-Gate NLDMOS

Pingrui Kang

Zhejiang University

Optimization of the Figure-Of-Merit in Drain-Extended MOS with a Salicide Block Structure

Xiaoyun Huang

Zhejiang University

Optimization of a Novel Integrated Zener Diode with Polysilicon Structure for Gate Protection in 55 nm BCD Technology

Pingrui Kang

Zhejiang University

Influence of Fluorine Implant on 3.3V NMOS Performance

Wu Tian

GHS Semiconductor Co., Ltd.

The Structural Optimization of LDMOS with Low-Temperature-Oxide Field Plate

Yixian Song

Zhejiang University

Design, Fabrication, and Process Optimization of Low-Voltage Super Junction Trench Gate MOSFET

Hongzhou Lu

University of the Chinese Academy of Sciences

Throughput Enhancement for Dual-Bit/Cell Split-Gate Floating-Gate Flash Memory Cell with Non-Self Aligned Process Technology

Zhang Yintong

HuaHong Grace Semiconductor Manufacturing Corporation

Investigation of the GIDL Current Shift Phenomenon in Symmetrical High-Voltage NMOS Devices On 55 nm Technology

Mingkang Yu

HuaHong Grace Semiconductor Manufacturing Corporation

Investigation and Optimization of Zener Diode in Advanced Process Node

Tian Tian

HuaHong Grace Semiconductor Manufacturing Corporation

Reducing Leakage Current of MOSFETs by Optimizing the Grain Size of Polysilicon Gate

Zhiyuan Long

HuaHong Grace Semiconductor Manufacturing Corporation

SRAM Device Threshold Voltage Mismatch Investigation and Improvement

Yangen Xie

GHS semiconductor

Research on Reducing Leakage in 2T SONOS Embedded Flash by Preamorphization Implant

Wenyu Guo

Shanghai Huali Microelectronics Corporation

Impact of X-ray Irradiation on Transfer Characteristics of Fin-FeFET Devices

Jiahao Yao

Institute of Microelectronics of the Chinese Academy of Sciences

The Influence of Writing Pulse on Memory Window of Fe-FinFET

Siyuan Liu

Institute of Microelectronics of the Chinese Academy of Sciences

Investigation of LDMOS Layout Optimization Utilizing Lithography Processes on 55nm Low Power Platform

Gang WANG

GHS Semiconductor

An 80 V P-Type Organic Semiconductor-Based Power Field-Effect Transistor Featuring a Stair Gate Dielectric Structure

Yi Qian

Nanjing University of Posts and Telecommunications

A Novel DNW Isolation Structure for Reducing Device Size

Houping Yang

Shanghai Huali Microelectronics Corporation

Study on Improving Local Mismatch of 0.305μm2 Small Size SRAM

Jingrong Kang

Shanghai Huali Microelectronics Corporation

3-D Mirror-Bit SONOS Memory Device with a Vertical-Channel Select Gate Transistor

Jingsong Peng

Shanghai HuaHong Grace Semiconductor Manufacturing Corporation

Time-dependence Dielectric Breakdown of Novel Dopant-Segregated Tunneling Field Effect Transistors Based on Foundry Platform

Jianfeng Hang

Peking University

Study on Improvement of FG Residue in NOR Flash by Etching Back

Jiayu Ma

Shanghai Huali Integrated Circuit Corporation

A Novel 8T TFET-MOSFET Hybrid SRAM Cell for Ultra-Low Power and Computing In-Memory Applications

Yingxi Zhou

Peking University

Flexible Beam Size Control Capability on Medium Current Implanter Accelerate CMOS Performance Improvement

Weilun Zeng

Applied Materials

Improving White Pixel Through the Optimization of Implantation Dose Rate in CIS Device

Jiayi Yang

Applied Materials

Effective Method to Improve Amplifier Constant β Performance for Advanced BCD

Helin Wang

Applied Materials

Device Performance Improvement by SuperScan3 Implant Application

Biao Sun

Applied Materials

Design of Ferroelectric FET-Based Symmetric Computing-in-Memory Array with Simultaneous Weight Gradient Calculation and Weight Update for On-Chip Learning

Yuxin Lin

Peking university

Implant Rs Monitor Recipe Parameters Optimizing with Digital Tool

Kui Shi

Applied Materials

The Multipole Effective Factors for High Current Implant Resistance Variation by Digital Mode Analysis

Jinsong Lin

Applied Materials

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Symposium I: Device Engineering and Memory Technology

Symposium I: Device Engineering and Memory Technology

Opening Remarks

Oral Session

Poster Session

Cryogenic CMOS: A New Era for Power-Saving Computing

Flip 3D (F3D): A dual-sided integration technology for future's computing hardware

Heterogeneous 3D CFET with Hybrid Channel Configuration

Performance Improvement of Monolithic CFET by Backside Enhanced Contact with C-type Source/Drain Contact Technology

A SiGe Channel Gate-All-Around Transistor Fabricated Using Novel Cyclic Self-Limiting Wet Etching Combined with Si Removal Process

A Novel Load-Si-cut SOI Nanosheets Transistors with Ultrathin SiGe Cladded Si Channel Structure to Suppress Leakage and Enhance Driven Current

The Intergration of SRAM-based Computing in Memory and DRAM-based Prcessing in Memory by 3D Stacking Techniques for AI Large Model Utilization

RRAM-based In-memory Computing for Intelligent Applications

Uncertainty Quantification on Multiscale Modeling of RRAM devices

Uniform, Large-Scale, and Robust PECVD-MoS2 Nanograined Memristors

Ferroelectric Materials, Devices and Chip Technologies for Enhanced Computational and Storage Capabilities

Hafnium-based Ferroelectric Memory and its Neuromorphic Computing Application

A NOVEL AMBIPOLAR FERROELECTRIC TUNNEL FINFET BASED COMPUTING-IN-MEMORY FOR QUANTIZED NEURAL NETWORKS WITH HIGH AREA- AND ENERGY-EFFICIENCY

Z2-FET MEMORY WITH BOTH FLASH AND DRAM MODES

Low-Frequency Noise of Vertical Gate-All-Around IGZO FETs

Defects Characterization and Their Impact on the Stability of Oxide Semiconductor Devices and 2T0C DRAM Cell

Electrical Characteristics of IGZO Thin Film Transistors Fabricated by Magnetron Sputtering with Controlled Mean Free Path of Sputtered Particles

Novel Low-Dimensional Material-Based Hot Carrier Transistors

Printable Organic Photodetectors for Spectrally Selective Light Sensing

Addressing Thermal Challenges in SOI with Silicon-On-Silicon Carbide Heterointegration

DC and RF Characteristics of Silicon FETs on 55nm Low Power Platform

Extract parameters from CV curves using a machine learning method

Advancing Semiconductor Industry through Atomistic Simulation: A Materials Design Perspective

Optimization of the Safe Operation Area in Step-Gate NLDMOS

Optimization of the Figure-Of-Merit in Drain-Extended MOS with a Salicide Block Structure

Optimization of a Novel Integrated Zener Diode with Polysilicon Structure for Gate Protection in 55 nm BCD Technology

Influence of Fluorine Implant on 3.3V NMOS Performance

The Structural Optimization of LDMOS with Low-Temperature-Oxide Field Plate

Design, Fabrication, and Process Optimization of Low-Voltage Super Junction Trench Gate MOSFET

Throughput Enhancement for Dual-Bit/Cell Split-Gate Floating-Gate Flash Memory Cell with Non-Self Aligned Process Technology

Investigation of the GIDL Current Shift Phenomenon in Symmetrical High-Voltage NMOS Devices On 55 nm Technology

Investigation and Optimization of Zener Diode in Advanced Process Node

Reducing Leakage Current of MOSFETs by Optimizing the Grain Size of Polysilicon Gate

SRAM Device Threshold Voltage Mismatch Investigation and Improvement

Research on Reducing Leakage in 2T SONOS Embedded Flash by Preamorphization Implant

Impact of X-ray Irradiation on Transfer Characteristics of Fin-FeFET Devices

The Influence of Writing Pulse on Memory Window of Fe-FinFET

Investigation of LDMOS Layout Optimization Utilizing Lithography Processes on 55nm Low Power Platform

An 80 V P-Type Organic Semiconductor-Based Power Field-Effect Transistor Featuring a Stair Gate Dielectric Structure

A Novel DNW Isolation Structure for Reducing Device Size

Study on Improving Local Mismatch of 0.305μm2 Small Size SRAM

3-D Mirror-Bit SONOS Memory Device with a Vertical-Channel Select Gate Transistor

Time-dependence Dielectric Breakdown of Novel Dopant-Segregated Tunneling Field Effect Transistors Based on Foundry Platform

Study on Improvement of FG Residue in NOR Flash by Etching Back

A Novel 8T TFET-MOSFET Hybrid SRAM Cell for Ultra-Low Power and Computing In-Memory Applications

Flexible Beam Size Control Capability on Medium Current Implanter Accelerate CMOS Performance Improvement

Improving White Pixel Through the Optimization of Implantation Dose Rate in CIS Device

Effective Method to Improve Amplifier Constant β Performance for Advanced BCD

Device Performance Improvement by SuperScan3 Implant Application

Design of Ferroelectric FET-Based Symmetric Computing-in-Memory Array with Simultaneous Weight Gradient Calculation and Weight Update for On-Chip Learning

Implant Rs Monitor Recipe Parameters Optimizing with Digital Tool

The Multipole Effective Factors for High Current Implant Resistance Variation by Digital Mode Analysis