Electronic Design Automation for Emerging Technologies
Giovanni De Micheli
EPFL Lausanne
Symposium IX: Design and Automation of Circuits and Systems
Symposium IX: Design and Automation of Circuits and Systems
-
Chip Level ESD/Latch-up Design Verification Automation
Frank Feng
Synopsys
DREAMPlace 3.X: Exploring Advanced Constraints and Multi-GPU Acceleration
Yibo Lin
Peking University
Stochastic Circuit Design Based on Exact Synthesis
Xiang He
Ningbo University
Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution
Masanori Hashimoto
Osaka University
Advancements on Parasitic Extraction Research and Related Challenges
Wenjian Yu
Tsinghua University
Improving Design Resilience Against Process and Voltage Variation
Wei-Kai Shih
Synopsys
Impact of Supply Noise on Nano-Meter VLSI Design: Hard or Soft Threshold?
Cheng Zhuo
Zhejiang University
Modeling of CMOS transistors from 0.18μm process by Artificial Neural Network
Jiahao Wei
Fudan University
Announcement of ACM SIGDA Eastern China Chapter
Cheng Zhuo
Zhejiang University, China
Ensuring System-Level Resilience for Embedded Systems
Ulf Schlichtmann
Technical University of Munich
Valid Test Pattern Identification for VLSI Adaptive Test
Tianming Ni
Anhui Polytechnic University
Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks
Grace Li Zhang
Technical University of Munich
Hardware/Software Co-Design of Deep Learning Accelerators
Yiyu Shi
University of Notre Dame
A LOW-BIT QUANTIZED AND HLS-BASED NEURAL NETWORK FPGA ACCELERATOR FOR OBJECT DETECTION
Jiaming Huang
Shanghai Jiao Tong University
A Multi-Core RISC-V Processor for CNN Accelerator
Zhang Li
Zhejiang University
On Device AI for AR Systems
Meng Li
Facebook Inc.
MAPPING CONVOLUTIONAL NEURAL NETWORKS ONTO NEUROMORPHIC CHIP FOR SPIKE-BASED COMPUTATION
Chenglong Zou
Peking University
Nonlinear quantization for in-memory multi-bit MAC in SRAM array
Shuo Chen
Zhejiang University
ApproxDNNFlow: An Evaluation and Exploration Framework for DNNs with Approximate Multipliers
Jide Zhang
Fudan University
A Novel Toffoli Gate Design Using Quantum-dot Cellular Automata
Huiming Tian
Ningbo University
Design of Ternary Logic Based on ReRAM Crossbars
Weiyi Liu
Shanghai Jiao Tong University
-
An Economic Layout Solution with 20 um Scribe Line and Integrated Test Pad Based on 55 nm Platform
Yang Zhao
HLMC
A MobileNet Accelerator with High Processing-Element Efficiency on FPGA
Tao Su
Sun Yat-sen University
Isolated word speech recognition based on BNN and its hardware implementation
刘鑫 Liu Xin
Peking University
Automated recognition of wafer backside image based on a hierarchical model
Junjun Zhuang
HLMC
A Homeostasis Based Expeditious Training Method in Spiking Neural Networks for Pattern Recognition
Guanbin Yang
Peking University
Optimizing the Energy Efficiency of Switched-Capacitor Converters in Multiprocessor System-on-Chips with a Preset DVFS Policy
Linfeng Zheng
ShanghaiTech University
Automatic Digital Modeling for Analog Blocks in Mixed-Signal Verification
Yangyang Leng
Tsinghua University
Sponsors:
