CMOS device design with ferroelectric materials
Changhwan Shin
Sungkyunkwan University
Symposium I: Device Engineering and Memory Technology
Symposium I: Device Engineering and Memory Technology
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Modeling of Ferroelectric FET
Kai Ni
Rochester Institute of Technology
High Performance Electronics Based on Ultrathin Novel Channel Materials
Yanqing Wu
Peking University
Si/SnS2 vertical heterojunction tunneling transistor with ionic-liquid gate for ultra-low power application
Liang Chen
Fudan University
Light-modulated Subthreshold Swing Effect in a MoS2-Si Hetero MOSFET
Yingxin Chen
Fudan University
Interconnect-centric Benchmarking of In-memory Acceleration for DNNs
Yu(Kevin) Cao
Arizona State University(ASU)
Smart Manufacturing of Si, SiC, GaN Power Devices in AI Era
Chi Min-hwa
SiEn (Qindao) Integrated circuits Cor
Trends and Challenges in Sensory Perception
Ming He
Peking University
A Novel Lightweight PUFs Using Interconnect Line Mismatch for Hardware Security
Yuejun Zhang
Ningbo University
Frontiers in Low-frequency Noise Research in Advanced Semiconductor Devices
Eddy Simoen
IMEC and University of Gent
FEOL Reliability in Gate-All-Around Nanosheet Devices (Invited) Nanosheet Devices (Invited)
Miaomiao Wang
IBM
Source/Drain contact technology for next generation semiconductor devices
Hyun-Yong Yu
Korea University
The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance
Wang Qingpeng
Coventor Inc., A Lam Research Company
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High-K Bubble Defect Researches in Stack-BSI Process Product
Zhuo Yin
Peking University
Super Junction by Implant Through Trench Contact for Low-Voltage Power MOSFET and IGBT
Janifer.liu
Impact of Contact Misalignment on Vt for Trench Power MOSFET
Perry.Li
SiEn (Qindao) Integrated circuits Cor.
Numerical Study of the VDMOS with an Integrated High-K Gate Dielectric and High-K Dielectric Trench
Zhenyu Zhang
Nanjing University of Posts and Telecommunications
Wafer Edge Crack Defect Investigation and Improvement In 19nm PSZ DEP Process
Junwei Han
HLMC
FinFET GGNMOS DC parameter variation understanding and ESD performance improvement solution by TCAD simulation
Hui Shen
Semiconductor Manufacturing International (Shanghai) Corporation
Effect of Floating-Gate Polysilicon Depletion on the Program/Erase Cycling Endurance Characteristics of 2y NAND Flash Memory
Jinho Kim
Dosilicon Co., Ltd.
Optimize The Cleaning Process of Tungsten Contact CMP to Avoid Copper Wire Bridges and Improve Product Yield
Jinfeng Wang
HLMC
FDSOI SiP Epitaxy Optimization For Leakage Reducing
Jiaqi Hong
HLMC
Etch back before ILD-CMP for improving the loading issue after ILD-CMP
Dongyangyang
HLMC
Research and improvement of residue defects in HK gate process based on CMP process
Duanqingqing
HLMC
The Effect of Different Well Implant Element on Different Pitch Size CMOS Image Senor
Li Xiaoyu
HLMC
Advance manufacturing process of LCOS based on Copper Reflector
GuoZhao
HLMC
The comprehensive solution of Ultra Top Metal stress impact on Seal Ring
LiuQIANG
HLMC
Demonstration of Full Well Capacity Monitoring and Optimizing through WAT Test
Lu Wang
HLMC
Improved method to analysis the doping profile for ion implants in silicon
Hui Chen
HLMC
Method of Reducing Metal Damager Defects in Back End of Line For Semiconductor in 28nm Technology
ShanshanChen
HLMC
Preheat Effect on Lamphead Pressure for 3D NAND Block Oxide Thickness Control
Yang Liu
Applied Materials (China), Inc. China
Applied Materials® RF PVD for DRAM Metal Gate Process Development
Jiachuan Wu
Applied Materials
Influence of Negative DIBL Effect on MOSFET Effective Drive Current and CMOS Circuit
Weixing Huang
Institute of Microelectronics of Chinese Academy of Sciences
Non-Linear Resistive Switching Characteristics in HfO2-based RRAM with Low-Dimensional Material Engineered Interface
Linbo Shan
Peking University
A Configurable Computing-in-Memory Structure Based on Convolutional Neural Network
Jiancheng Yang
Peking University
Engineering of substrate oxidation in deposited SiC Gate stacks for improving interface performance
Shuo Liu
Shanghai Jiao Tong University
Improvement of RRAM Uniformity and Analog Characteristics through Localized Metal Doping
Yabo Qin, Zongwei Wang*, Qingyu Chen, Yaotian Ling, Lindong Wu, Yimao Cai*,Ru Huang
Peking University
Impacts of Ferroelectric Parameters on the Electrical Characteristics of FeFET for Low-power Logic and Memory Applications
Kaifeng Wang
Peking University
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