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Symposium II: Lithography and Patterning

Symposium II: Lithography and Patterning

Virtual Conference Registration
  • Download Agenda
  • CSTIC 2022 Call for Papers

Opening Remarks

  • Dr. Leo Pang

    Chief Product Officer

    D2S

    View
  • Oral Session

  • Poster Session

  • Advanced Packaging Architectures for Advanced Heterogeneous Integration (HI)

    Ravi Mahajan

    Intel

    Negative-tone imaging (NTI) for advanced lithography with EUV exposure to improve 'Chemical Stochastic'

    TORU FUJIMORI

    FUJIFILM Corporation

    Progress and outlook towards High-NA EUV materials

    Jara Garcia Santaclara

    ASML

    HIGH PERFORMANCE BULK AND POU FILTRATION OF EUV LITHOGRAPHY MATERIALS

    Lucia D’Urzo

    Pall

    Development of planarizing spin-on carbon material for high-temperature processes

    Runhui Huang

    Brewer Science Inc.

    Contour based process characterization, control and hotspot prediction for semiconductor manufacturing

    AO CHEN

    Mentor, a Siemens Business

    The Setting of Linewidth Reference on Photomask through Physical Process Modeling

    Rui Hu

    ICRD

    SEM Image Transformation between Litho Domain and Etch Domain

    Yan Yan

    ICRD

    ML enhanced full-flow design guided wafer defect analysis and reduction

    Qian Xie

    Mentor, a Siemens Business

    Full Chip Curvilinear ILT with both Multi-Beam and VSB Mask Writers That Doubles Wafer Process Windows

    Leo Pang

    D2S

    Optical Proximity Correction (OPC), Methodology and Limitations

    Yongqiang Hou

    ICRD

    Update of >300W High Power LPP-EUV Source Challenge III for Semiconductor HVM

    Hakaru Mizoguchi

    Gigaphoton

    193i lithography’s path to the future

    Stephen Renwick

    Nikon Research Corp of America

    Nanoimprint Performance Improvements for High Volume Semiconductor Manufacturing

    Keita Sakai

    Canon Inc.

    Extending the capability of lithography with mechanical processes

    Huigao Duan

    Hunan University

    An innovative graphical platform for real time accurate AEI overlay prediction and rework control

    Xue Huang

    YMTC

    A New Generation Cost-efficient Laser Mask Writer for Mature Semiconductor Nodes

    Peter Henriksson

    Mycronic AB

    Reference Metrology Using 3D-PSD of Post-Etch LWR

    Masami Ikota

    Hitachi High-Tech Corp.

    Feed-forward correction of on-product overlay using standalone alignment technology

    Masahiko OKUMURA

    Nikon Corporation

    Overlay metrology based on Mueller matrix scatterometry

    Hao Jiang

    Huazhong University of Science and Technology

  • The photoresist developing ability study at different contact angle and mask transmission rate

    Chen Lijun

    Shanghai Huali Microelectronics Corporation

    The Mechanism Study of Rounded AA Damage Defect after POLY Loop

    Zheng Haichang

    Shanghai Huali Microelectronics Corporation

    Contour extraction for SEM image based on deep learning method

    Li Chen

    Shanghai IC R&D Center

    Extreme edge uniformity control study in Poly-Si Planarization etch

    Minxiang Wang

    Lam Research Service Co., Ltd

    Mining Lithography Hotspots from Massive SEM Images Using Machine Learning Model

    Zhou Tao

    Shanghai IC R&D Center

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