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Symposium IX: Design and Automation of Circuits and Systems

Opening Remarks

Weikang Qian

University of Michigan-Shanghai Jiao Tong University Joint Institute, China
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Oral Session
Poster Session

Design Tools for Adiabatic Quantum-Flux-Parametron Logic: Toward Extremely Energy-Efficient Computing

Tsung-Yi Ho

Chinese University of Hong Kong

Logic synthesis and some of its challenges

Yong Xiao

Giga Design Automation Co., Ltd.

Essential Steps to Analyze Effective Resistance of ESD Paths-PG Routing Network Pruning and Resistance Contribution by Layer

Frank Feng

Synopsys

Logic Circuit Simulation based on Semi-Tensor Product

Zhufei Chu

Ningbo University

CirSAT: An Efficient Circuit-based SAT Solver via Fanout-driven Decision Heuristic

Zhufei Chu

Ningbo University

RLCkt: An Analog Circuit Automatic Sizing Sage Based on Reinforcement Learning

Wangge Zuo

Fudan University

Compute-in-ROM: How to Achieve Both High Density and High Flexibility?

Xueqing Li

Tsinghua University

Break the Memory Wall: Cross-Layer Co-Design for Energy Efficient Machine Learning SoCs

Chixiao Chen

Fudan University

STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell for AI Inference

Hao Cai

Southeast University

CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation

Grace Li Zhang

Technical University of Munich

Co-Design of Binarized Deep Learning

Zhiru Zhang

Cornell University

Efficient Deep Learning Accelerators Based on Multimodal Model Compression

Jun Lin

Nanjing University

Efficient Multi-Modal AI Acceleration

Meng Li

Facebook Inc.

Efficient partitioning and communication scheme based distributed edge computing to accelerate deep neural network

Xudong Lu

Zhejiang University

Post-training Quantization or Quantization-aware Training? That is the Question

Xiaotian Zhao

Shanghai Jiao Tong University

Ultra-Fast FPGA Acceleration of Graph Cut Algorithms

Yajun Ha

ShanghaiTech University

Integrated System Design for Neural Radiance Field Rendering

Xin Lou

ShanghaiTechUniversity

Real-time Scheduling of Hard Deadline Tasks on a Heterogeneous Architecture

An Zou

Shanghai Jiao Tong University

Agile Sign-Off for Sub-Nanometer VLSI Designs in the Post-Moore Era

Cheng Zhuo

Zhejiang University

Learning Based Electromigration Induced Stress Evolution Analysis for Multi-segment Interconnect Wires

Haibao Chen

Shanghai JiaoTong University

Artificial Neural Network Compact Modeling Methodology for Complementary Field Effect Transistor (CFET)

Owen Tao

Fudan University

An 18-Bit 2MSPS SAR ADC with Double Passive Noise-Shaping Calibration

Xiaowei Zhang

Zhejiang University

A 2A 4MHz Dual-Phase ZDS Hysteretic DC-DC Buck Converter with Peak Efficiency above 90%

Yanye Chen

Zhejiang University
Design and simulation of a PFM-PWM hybrid controller for DCDC converter with CLLC topology

Hai Liu

Zhejiang University

Improve SIP via Incomplete Cholesky Factorization

Yang Yang

Fudan University

High Efficient Automatic Power/Ground Layout Routing algorithm for Analog ICs

Jiaxin Zuo

Fudan University

Implementing Boolean Function by Ternary Content Addressable Memory with Approximate Match

Jian Shi

Shanghai Jiao Tong University

Verification of 100Gb/s Data-Rate Transceiving through Silicon-Photonic Module in an FPGA Platform

C.-Z. CHEN

Peng Cheng Laboratory

A 14.7mW 4Gbslane Wireless Through Silicon Interface for Memory Cube exploiting 16-QAM and Magnetic Resonance

Chonghui Sun

Zhejiang University

A Hardware Accelerator for Standard Convolution and Depthwise Convolution

Fubang An

Fudan University

A Multi-layer stacked 3-D SRAM system based on wireless transceiver using inductively coupled interface in 22-nm CMOS

Kun Yang

Zhejiang University

An Adaptive Controlled Chip-level Wireless Power Transfer System with DPID Controller for Wireless 3-D Stacked Chips

Rushuo Tao

Zhejiang University

A Front-end for 1.5GSPS 12bit Pipelined ADC

Xiuheng Wu

Institute of Microelectronics, Chinese Academy of Sciences

Security concerns over the cloud-oriented EDA solution

Shiyue Qin

Northeastern University

LUTPlace: An Improved Lookup Table-Based Placement for Routability

Yihang Qiu

Guangdong University of Technology

AcArm: A Novel Semiconductor Wafer Handling Robot

Donglin Chen

Northeastern University

Attention-based Mechanism for Technology Mapping Optimization

Zhaohui Yang

Ningbo University

An efficient ATPG technology based on Time Division Multiplexing method

Zhou Lunmao

Sanechips Technology Co., Ltd

A high-sensitivity and large-dynamic range readout circuit for polysilicon-based microbolometer

Wei Zhu

Nanjing University

Parallelizable Interval graph-based Branch-Cut algorithm for placement problems in VLSI

Jiefu Yang

Northeastern University

A Scalable And Configurable Low-Power Mixed Signal Neuromorphic Accelerators For Spiking Neural Network

Yekuan Chen

Zhejiang University

Convolutional Neural Networks on the Edge: A Comparison Between FPGA and GPU

Xinfei Guo

University of Michigan–Shanghai Jiao Tong University Joint Institute

A 2-D Multi-dielectric Capacitance Solver Based on Floating Random Walk Method

Jiahao Xu

Tsinghua University

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Symposium IX: Design and Automation of Circuits and Systems

Symposium IX: Design and Automation of Circuits and Systems

Opening Remarks

Weikang Qian

Oral Session

Poster Session

Design Tools for Adiabatic Quantum-Flux-Parametron Logic: Toward Extremely Energy-Efficient Computing

Logic synthesis and some of its challenges

Essential Steps to Analyze Effective Resistance of ESD Paths-PG Routing Network Pruning and Resistance Contribution by Layer

Logic Circuit Simulation based on Semi-Tensor Product

CirSAT: An Efficient Circuit-based SAT Solver via Fanout-driven Decision Heuristic

RLCkt: An Analog Circuit Automatic Sizing Sage Based on Reinforcement Learning

Compute-in-ROM: How to Achieve Both High Density and High Flexibility?

Break the Memory Wall: Cross-Layer Co-Design for Energy Efficient Machine Learning SoCs

STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell for AI Inference

CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation

Co-Design of Binarized Deep Learning

Efficient Deep Learning Accelerators Based on Multimodal Model Compression

Efficient Multi-Modal AI Acceleration

Efficient partitioning and communication scheme based distributed edge computing to accelerate deep neural network

Post-training Quantization or Quantization-aware Training? That is the Question

Ultra-Fast FPGA Acceleration of Graph Cut Algorithms

Integrated System Design for Neural Radiance Field Rendering

Real-time Scheduling of Hard Deadline Tasks on a Heterogeneous Architecture

Agile Sign-Off for Sub-Nanometer VLSI Designs in the Post-Moore Era

Learning Based Electromigration Induced Stress Evolution Analysis for Multi-segment Interconnect Wires

Artificial Neural Network Compact Modeling Methodology for Complementary Field Effect Transistor (CFET)

An 18-Bit 2MSPS SAR ADC with Double Passive Noise-Shaping Calibration

A 2A 4MHz Dual-Phase ZDS Hysteretic DC-DC Buck Converter with Peak Efficiency above 90%

Design and simulation of a PFM-PWM hybrid controller for DCDC converter with CLLC topology

Improve SIP via Incomplete Cholesky Factorization

High Efficient Automatic Power/Ground Layout Routing algorithm for Analog ICs

Implementing Boolean Function by Ternary Content Addressable Memory with Approximate Match

Verification of 100Gb/s Data-Rate Transceiving through Silicon-Photonic Module in an FPGA Platform

A 14.7mW 4Gbslane Wireless Through Silicon Interface for Memory Cube exploiting 16-QAM and Magnetic Resonance

A Hardware Accelerator for Standard Convolution and Depthwise Convolution

A Multi-layer stacked 3-D SRAM system based on wireless transceiver using inductively coupled interface in 22-nm CMOS

An Adaptive Controlled Chip-level Wireless Power Transfer System with DPID Controller for Wireless 3-D Stacked Chips

A Front-end for 1.5GSPS 12bit Pipelined ADC

Security concerns over the cloud-oriented EDA solution

LUTPlace: An Improved Lookup Table-Based Placement for Routability

AcArm: A Novel Semiconductor Wafer Handling Robot

Attention-based Mechanism for Technology Mapping Optimization

An efficient ATPG technology based on Time Division Multiplexing method

A high-sensitivity and large-dynamic range readout circuit for polysilicon-based microbolometer

Parallelizable Interval graph-based Branch-Cut algorithm for placement problems in VLSI

A Scalable And Configurable Low-Power Mixed Signal Neuromorphic Accelerators For Spiking Neural Network

Convolutional Neural Networks on the Edge: A Comparison Between FPGA and GPU

A 2-D Multi-dielectric Capacitance Solver Based on Floating Random Walk Method