Scale-out Chiplet-based Systems: Architecture, Design and Pathfinding
Puneet Gupta
University of California, Los Angeles(UCLA)
Symposium IX: Design and Automation of Circuits and Systems
Symposium IX: Design and Automation of Circuits and Systems
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Photonic-Electronic Design Automation
Jiang Xu
Hongkong University of Science and Technology
Diffusive/Quantum Carrier Transport and Multiphysics Simulation Methods of Advanced Electronic/Optoelectronic Devices
Wenchao Chen
Zhejiang University
Design Technology Co-Optimization Methods for Advanced Logic Nodes
Xingsheng Wang
Huazhong University of Science and Technology
Machine Learning for Device Modeling (MLDM) in the DTCO Eco-system
Lining Zhang
Peking University
Exploring AI-in-the-Loop For Physical Design Verification DFM/DTCO EDA
Yongfu Li
Shanghai Jiao Tong University
Ultra-broadband RF Front-end SoC using 0.18um CMOS technology
Jianguo Ma
Zhejiang Lab
Logic Locking over TFHE for Securing User Data and Algorithms
Masanori Hashimoto
Kyoto University
A Customized Model for Defensing Against Adversarial Attacks
Jiang Sun
ShanghaiTech University
Logic Synthesis based on Semi-tensor Product of Matrices
Zhufei Chu
Ningbo University
Logic Synthesis for XOR-AND Graphs via Reed-Muller Representations
Zhufei Chu
Ningbo University
Integration of Shift Left Updates into Logic Synthesis and Macro Placement
Xinfei Guo
Shanghai Jiao Tong University
TimingDTH: Timing-driven placement with Deep Three-Head reinforcement learning
Shuai Yuan
Shanghai Jiao Tong University
Decoupling Capacitor Optimization for 2.5D-ICs with Deep Reinforcement Learning Technique
Haiyang Feng
Zhejiang University
Optimizing Architecture and Algorithm for Privacy-Preserving Machine Learning
Jongeun Lee
Ulsan NationalInstitute of Science and Technology
Efficient and Robust Hardware for Neural Networks
Li Zhang
Technical University of Darmstadt
Algorithm and Hardware Codesign for Brain-inspired Neuromorphic Computing
Aili Wang
Zhejiang University
A Hardware Accelerator for Sparse Computing Based on NVDLA
Yizhou Chen
Zhejiang University
Integer Arithmetic-Based and Activation-Aware GELU Optimization for Vision Transformer
Zihan Zou
Southeast University
TBD
Xunzhao Yin
Zhejiang University
Navigating Aging Effects: Concepts and Implementation in Reliable Computing Systems
Yu-Guang Chen
National Central University
Enhance the Real-Time Performance of FPGA through Partial Dynamic Reconfiguration
An Zou
Shanghai Jiao Tong University
A 16-bit 8MSPS SAR ADC with Configurable Low-Power Comparator
Yidan Liang
Zhejiang University
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Data Flow Graph Partitioning Method for CGRA Temporal Mapping Based on Bayesian Optimization
Yihan Hu
Fudan University
Verification of 400GbE with Optical Modules on an FPGA Platform
C.-Z. CHEN
Peng Cheng Laboratory
A transient enhanced output capacitor-less LDO with adaptive biasing and spike reduction
Qianxi Cheng
Peking University
DESIGN OF A 10BITS 100MSPS SAR ADC
Chaorun Li
Peking University
Runtime Configurable Approximate Computing System for Simulated Annealing Algorithm
Shi Jian
Shanghai Jiao Tong University
Effective Resistance Estimation for Large Circuits Using Random Walk Algorithm
Jinyu Zhang
Empyrean Technology Co., Ltd
Designing and Accelerating Spiking Neural Network based on High-level Synthesis
Heng Zi
Beijing University of Posts and Telecommunications
STOCHASTIC COMPUTING HARDWARE DESIGN AND OPTIMIZATION FOR CONVOLUTIONAL NEURAL NETWORKS
Zhinan Chen
Fudan University
A 106TOPS/W SRAM Compute-In-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI
Yiqi Meng
Zhejiang University
Application of Community Detection based Parallel MOEA/D Algorithm in RF Power Amplifier Circuit Design
Jiejin Zhou
Fudan University
A Hardware Accelerator of the Convolutional Spike Neural Network Based on STDP Online Learning
Qinxin Chen
Zhejiang University
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