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Conference of Science & Technology for Integrated Circuits (CSTIC) 2025

集成电路科学技术大会(CSTIC) 2025

Conference of Science & Technology for Integrated Circuits (CSTIC) 2025

集成电路科学技术大会(CSTIC) 2025

  • CSTIC 2026 Call for Papers
  • Committees
  • Keynote Speakers
  • Training Courses
  • Symposiums
  • Sponsors

Welcome to CSTIC 2025, one of the largest and the most comprehensive annual semiconductor technology conferences in China and Asia since 2000. Organized by SEMI and IEEE, co-organized by Institute of Microelectronics, Chinese Academy of Sciences and SAMT. CSTIC 2025 was held on March 24-25, 2025 in Shanghai, China, in conjunction with SEMICON China 2025. Virtual conference will be held on April 2-30 at SEMI Cloud. The conference will have ten symposiums covering all aspects of semiconductor technology with focus on manufacturing and advanced technology, including detailed manufacturing processes, device design, integration, materials, and equipment, as well as emerging semiconductor technologies, circuit design, and silicon material applications. Hot topics, such as artificial intelligence (AI) chips, 6G chips, neuromorphic computing technology, advanced memory technology, 3D integration, MEMS technology will also be addressed in the conference.

**Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore's scope and quality requirements.

Plenary Session

Committees More

  • Dr. Beichao Zhang

    Conference Chair

    Hangzhou GHS Semiconductor

  • Prof. Bin Yu

    Conference Executive Co-Chair

    Zhejiang University

  • Dr. Peng Bai

    Conference Co-Chair

    HHGrace, China

  • Prof. Cor Claeys

    Conference Co-Chair

    KU Leuven, Belgium

  • Dr. Steve X. Liang

    Conference Co-Chair

Keynote Speakers More

Heterogeneous Computing Solutions for Power-Performance Efficient On-Device AI

Dr. Giri Nallapati

CEO, Qualcomm Inc., USA

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From the Nanometer Scale to Light Years

Dr. Edmundo A. Gutiérrez D.

General Director, INAOE, Mexico

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Chip Design for AI and AI for Chip Design

Dr. Tim Kwang-Ting Cheng

Vice-President for Research and Development, The Hong Kong University of Science and Technology, China

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Materials Engineering Innovations to Address Next-Gen Electronics Packaging Challenges

Mr. Terrance Lee

Corporate Vice President, GM, Applied Materials, USA

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Sponsors:
Organizer:
Co-Organizer:

Training Courses More

  • 2106

    Photolithography and Related Technologies and Process Standards

     Prof. Qiang Wu Professor, Fudan University
  • 2108

    Advanced Package and 3DIC (Chiplets and HBM)

     Dr. Guorong Li Vice President, Beijing NAURA Technology Group Co., Ltd.
  • 2111

    Advanced Package and 3DIC (Chiplets and HBM)

     Dr. Xia Jiang Chief Scientist, JCET Semiconductor Integration (Shaoxing) Co., Ltd., China

Parallel Symposiums

  • Symposium I: Device Engineering and Memory Technology
  • Symposium II: Lithography and Patterning
  • Symposium III: Dry & Wet Etch and Cleaning
  • Symposium IV: Thin Film, Plating and Process Integration
  • Symposium V: CMP and Cleaning
  • Symposium VI: Metrology, Reliability and Testing
  • Symposium VII: Packaging and Assembly
  • Symposium VIII: MEMS, Sensors and Emerging Semiconductor Technologies
  • Symposium IX: Design and Automation of Circuits and Systems
  • Symposium X: AI & IC Manufacturing

Sponsor Video

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